1. Field of the Invention
This invention relates to co-packaged semiconductor devices and more specifically to a decoupling circuit to prevent the noise generated in one co-packaged die from affecting the operation of other co-packaged dice. As understood by those in the art, to “co-package” means to assemble two or more dice in the same package.
2. Relevant Art
It is well known to co-package diverse semiconductor dice on a common board or in a common housing. For example, co-packaging of MOSFETS or IGBTS with gate drivers and other related circuit elements in multichip modules can reduce the effects of printed circuit board layout on the performance of power factor correction (PFC) circuits and dc-dc converters, and can reduce EMI, switching losses and conduction losses. It can also reduce PCB area, thus allowing achievement of higher power density, while reducing component count and the time and cost of assembly.
Examples of co-packaged circuits may be found in commonly assigned U.S. Pat. Nos. 6,740,902, 6,404,050, 6,297,552, 6,133,632, and 5,814,884, and in published U.S. patent application 2004-0169262.
The benefits of co-packaging, however, come at a price: the potential for noise coupling between the co-packaged elements is significantly increased. For example, an IGBT can produce high di/dt when switching on and off, which can affect the operation of co-packaged dice, such as, a closely mounted integrated circuit power factor correction (PFC) integrated circuit or chip.
FIG. 1 shows a semiconductor die 10 which may, for example, be a power transistor such as an IGBT or a MOSFET. This is comounted on a common board or within a common housing with an integrated circuit (IC) 11, which may be a power factor control (PFC) circuit or other circuit which provides control and gate drive for device 10. For convenience, the invention will be described in the context of an IGBT as device 10 and a PFC circuit as device 11, but it is to be understood that the principles of the invention apply as well to other co-packaged devices which are susceptible to noise coupling.
Referring still to FIG. 1, emitter E of the IGBT 10 is coupled to the substrate of IC 11 by a parasitic capacitance 12 (for example, 1.2 PF), associated with an insulating film, formed, for example of a polyimide such as Kapton®. There is also a parasitic lead inductance L1 through which the IC is grounded.
FIG. 2 shows the IC 11 and IGBT 12, along with circuit components to define a conventional PFC circuit, including an inductor 20 and diode 21. The collector 50 of IGBT 10 is connected to a node 22 between inductor 20 and diode 21, and its emitter 52 is connected to ground through a parasitic inductance L2 which represents lead, wire-bond, package, and PCB parasitic inductances. FIG. 2 also shows the parasitic capacitance 12 associated with the insulation layer (see FIG. 1). The voltage resulting from large values of di/dt associated with fast switching of IGBT 10 is coupled back through parasitic capacitance 12 to IC 11 as noise.
One way to reduce such noise is to provide a properly designed decoupling circuit, but for this to he effective, the noise source and noise pats must be modeled, i.e. defined and/or simulated based on theoretical parameters, correctly. Up to now, decoupling circuits have been used on single, i.e., individual ICs, but inter-dice noise modeling and use of a decoupling circuit on one IC to dampen the effect of noise from another co-packaged IC has not been done, so far as I am aware. The present invention permits such modeling for closely positioned co-packaged chips or dice.